Atmel’s FPSLIC II Dynamically Reconfigurable SoC Supports “Silicon-Sharing” For Peripherals & Interfaces

Atmel Corporation (NASDAQ: ATML) today introduced its AVR-based FPSLIC II, the industry’s first family of dynamically reconfigurable systems-on-chips (SoCs) that allows multiple interfaces, peripherals and/or operators to share the same silicon at different times.

“Silicon sharing” is extremely important in power- and space-constrained systems, such as new generation cell phones, PDAs, notebook computers, and printer/fax machines. Increasingly these devices must perform multiple functions (e.g. camera, MP3 player, phone) without sacrificing battery life, product size or product cost.

FPSLIC II’s silicon-sharing capability is enhanced by Atmel’s back-end EDA tools, Reconfiguration Designer and Temporal Designer . The tools are the first to automate the implementation, timing, and control of the silicon-sharing process. Previously, the design of silicon-sharing systems was essentially impossible because, even though many FPGAs can be reconfigured during operation, until now, there have been no tools to automate reconfiguration control and timing. Atmel is the first programmable SoC vendor to provide such EDA support.

The FPSLIC II dynamically reconfigurable programmable SoC integrates a 40 MIPS, 8-bit AVR processor, with 36 KB program/data SRAM, a hardware multiplier, peripherals and a dynamically reconfigurable FPGA, with 256 to 2300 core cells. A single piece of silicon can implement multiple, interchangeable peripherals, computational operators, and bus interfaces, including SDIO, PCI, PCMCIA, HDLC, and Ethernet.

The main obstacles to silicon-sharing has always been ensuring that the correct functionality is loaded into the FPGA at the correct time and that functions are not loaded on top of each other. Since either of these can cause catastrophic system failure, adding new features has typically required the addition of dedicated silicon (i.e. a larger FPGA), increasing both power consumption and system cost. Atmel has solved this problem by placing a configuration controller, two DMA controllers, a dedicated FPGA-to-AVR interface and a “virtual socket” in the FPGA portion of the programmable SoC. The “virtual socket” is populated from a library of previously designed peripherals, interfaces or operators that share the same silicon.

Atmel provides a library of reference designs for interfaces, peripherals and hardware accelerators that includes Ethernet, memory, SPI, SDIO, multimedia card, DMA, speech synthesis, ADPCM, audio codec interfaces, and DES/triple DES encryption algorithms. The company will introduce a library of pre-routed “drag-and-drop” co-processors and interfaces later this year. Designers may also use Atmel’s System Designer EDA tool to develop custom IP for silicon sharing.