NXP LPC32x0 32位ARM嵌入方案

NXP公司的LPC32x0 16/32位 ARM9微控制器具有硬件浮点协处理器，USB OTG以及EMC存储器接口，32KB指令缓存和32KB数据缓存，是一个通用的ARM926EJ-S 32位微处理器。LPC32x0系列可工作在高于200MHz的CPU频率下。LPC32x0系列还包含有256kB的片内静态RAM、1个NAND Flash接口、1个以太网MAC、1个支持STN和TFT面板的LCD控制器、1个支持SDR和DDR SDRAM以及静态设备的外部总线接口。此外，LPC32x0系列包括1个USB2.0全速接口、7个UART、2个I2C接口、2个SPI/SSP端口、2个I2S接口、2个多通道PWM、4个带有捕获输入和比较输出的通用定时器、1个加密数字（SD）接口和1个带有触屏感应选项的10位A/D转换器。可提供高性能和非常低的功耗，广泛应用在消费类电子，汽车电子，医疗仪器设备，网络控制和工业领域。本文介了LPC32x0系列的主要性能和方框图。


NXP Semiconductor designed the LPC32x0 family for embedded applications requiring
high performance combined with low power consumption.
NXP achieved their performance goals using 90 nanometer process technology to
implement an ARM926EJ-S CPU core with a Vector Floating Point co-processor and a
large set of standard peripherals including USB On-The-Go. Figure 1 shows a block
diagram of the LPC32x0 family. The LPC32x0 family operates at CPU frequencies
exceeding 200 MHz. The basic ARM926EJ-S CPU Core implementation uses a Harvard
architecture with a 5-stage pipeline. The ARM926EJ-S core also has an integral Memory
Management Unit (MMU) to provide the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The basic ARM926EJ-S core also includes a set of DSP instruction extensions including single cycle MAC operations and native Jazelle Java Byte-code execution in hardware. The NXP implementation has a 32 KB Instruction Cache and a 32 KB Data Cache.
For low power consumption, the LPC32x0 family takes advantage of NXP
Semiconductors advanced technology development to optimize Intrinsic Power, and uses software controlled architectural enhancements to optimize application based Power Management.

The LPC32x0 family also includes 256 KB of on-chip static RAM, a NAND Flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC32x0 family includes a USB 2.0 Full Speed interface, seven UARTs, two I2C interfaces, two SPI/SSP ports, two I2S interfaces, two multi-channel PWMs, four general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit A/D converter with a touch screen sense option.

主要特性：
ARM926EJS processor, running at CPU clock speeds up to 208 MHz
A Vector Floating Point coprocessor.
A 32 KB instruction cache and a 32 KB data cache.
Up to 256 KB of internal SRAM (IRAM).
Selectable boot-up from various external devices: NAND Flash, SPI memory, USB,
UART, or static memory.
A Multi-layer AHB system that provides a separate bus for each AHB master, including
both an instruction and data bus for the CPU, two data busses for the DMA controller,
and another bus for the USB controller, one for the LCD and a final one for the
Ethernet MAC. There are no arbitration delays in the system unless two masters
attempt to access the same slave at the same time.
An External memory controller for DDR and SDR SDRAM, as well as static devices.
Two NAND Flash controllers. One for single level NAND Flash devices and the other
for multi-level NAND Flash devices.
A Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC),
supporting 74 interrupt sources.
An eight channel General Purpose AHB DMA controller (GPDMA) that can be used
with the SD card port, the high-speed UARTs, I2S ports, and SPI interfaces, as well as
memory-to-memory transfers.
Serial Interfaces:
A 10/100 Ethernet MAC with dedicated DMA Controller.
A USB interface supporting either Device, Host (OHCI compliant), or On-The-Go
(OTG) with an integral DMA controller and dedicated PLL to generate the required
48 MHz USB clock.
Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One
of the standard UART’s supports irDA.
Three additional high-speed UARTs intended for on-board communications that
support baud rates up to 921,600 bps when using a 13 MHz main oscillator. All
high-speed UARTs provide 64-byte FIFOs.
Two SPI controllers.
Two SSP controllers.
Two I2C-bus Interfaces with standard open drain pins. The I2C-bus Interfaces
support single master, slave and multi-master I2C configurations.
Two I2S interfaces, each with separate input (RX) and output (TX) channels. Each
channel can be operated independently on 3 pins, or both input and output
channels can be used with only 4 pins and a shared clock.
Additional Peripherals:
LCD controller supporting both STN and TFT panels, with dedicated DMA
controller. Programmable display resolution up to 1024x768.
Secure Digital (SD) memory card interface, which conforms to the SD Memory
Card Specification Version 1.01.
General purpose input, output, and I/O pins. Includes 12 GP input pins, 24 GP
output pins, and 51 GP I/O pins.
10 bit, 400kHz A/D Converter with input multiplexing from 3 pins. Optionally, the
A/D Converter can operate as a touch screen controller.
Real Time Clock (RTC) with separate power pin. This RTC has a dedicated 32 kHz
oscillator. NXP implemented the RTC in an independent on-chip power domain so
it can remain active while the rest of the chip is not powered. The RTC also
Includes a 32 byte scratch pad memory.
A 32-bit general purpose high speed timer with a 16-bit pre-scaler. This timer
includes one external capture input pin and a capture connection to the RTC clock.
Interrupts may be generated using 3 match registers.
Four enhanced Timer/Counters which are identical except for the peripheral base
address. A minimum of two Capture inputs and two Match outputs are pinned out
for all four timers, with a choice of several pins for each. Timer 1 brings out a third
Match output, while Timers 2 and 3 bring out all four Match outputs.
A 32-bit Millisecond timer driven from the RTC clock. This timer can generate
Interrupts using 2 match registers.
A Watchdog Timer. The watchdog timer is clocked by PERIPH_CLK.
Two versatile PWM blocks with 6 and 4 outputs respectively, programmable
resolution, and an external clock capability.
Two additional single output PWM blocks.
Keyboard scanner function allows automatic scanning of up to an 8x8 key matrix.
Up to 18 external interrupts.
Standard ARM Test/Debug interface for compatibility with existing tools.
Emulation Trace Buffer with 2K x 24 bit RAM allows trace via JTAG.
Stop mode saves power, while allowing many peripheral functions to restart CPU
activity.
On-chip crystal oscillator.
An on-chip PLL allows CPU operation up to the maximum CPU rate without the
requirement for a high frequency crystal. Another PLL allows operation from the 32
kHz RTC clock rather than the external crystal.
Boundary Scan for simplified board testing.
296 pin TFBGA package.
主要应用：
Consumer
Automotive
Medical
Network Control
Industrial



图1.LPC32x0系列方框图