NS ADC10D1000超高速ADC方案

NS公司的ADC10D1000是超高速低功耗10位ADC,单路速率可达到2.0GSPS,或双路1.0GSPS,.单电源1.9V ± 0.1V,功耗小于2.8W. ADC10D1000主要用于宽带通信,数据采集系统和数字示波器.本文介绍了ADC10D1000的主要特性格和指标,方框图和在温度传感器中的应用框图.

ADC10D1000: Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter

The ADC10D1000 is the latest advance in Nationals Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0 GSPS (Non-DES Mode) or for a single channel up to 2.0 GSPS (DES Mode). The ADC10D1000 achieves excellent accuracy and dynamic performance while dissipating less than 2.8 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package which does not require a heat sink over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.0 Effective Number of Bits (ENOB) with a 498 MHz input signal and a 1.0 GHz sample rate while providing a 10 -18 Code Error Rate (CER) Dissipating a typical 2.8 Watts in Non-Demultiplex Mode at 1.0 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or twos complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

ADC10D1000主要特性:
■Excellent accuracy and dynamic performance
■Low power consumption
■Internally terminated, buffered, differential analog inputs
■R/W SPI Interface for Extended Control Mode
■Dual-Edge Sampling Mode, in which the I- and Q-channels sample one input at twice the sampling clock rate
■Test patterns at output for system debug
■Programmable 15-bit gain and 12-bit plus sign offset
■1:1 non-demuxed or 1:2 demuxed LVDS outputs
■AutoSync feature for multi-chip systems
■Single 1.9V ± 0.1V power supply
■292-ball BGA package (27mm x 27mm x 2.4mm with
1.27mm ball-pitch); no heat sink required
■LC sampling clock filter for jitter reduction
ADC10D1000主要指标:
(Non-Demux Non-DES Mode, Fs=1.0 GSPS, Fin = 248 MHz)
■Resolution 10 Bits
■Conversion Rate
—Dual channels at 1.0 GSPS (typ)
—Single channel at 2.0 GSPS (typ)
■Code Error Rate 10-18 (typ)
■ENOB 9.1 bits (typ)
■SNR 56.7 dBc (typ)
■SFDR 66 dBc (typ)
■Full Power Bandwidth 2.8 GHz (typ)
■DNL ±0.2 LSB (typ)
■Power Consumption
—Single Channel Enabled 1.61W (typ)
—Dual Channels Enabled 2.77W (typ)
—Power Down Mode 59 mW (typ)
ADC10D1000应用:
■Wideband Communications
■Data Acquisition Systems
■Digital Oscilloscopes



图1.ADC10D1000方框图



图2.ADC10D1000在温度传感器中应用