Wireless IC technology continues to evolve

As more and more wireless technologies become available in the marketplace (making them almost ubiquitous), users are demanding devices and services that automatically use the best available technology. Making things simpler, cheaper, and widely available are really what consumers are striving for. As we move into the technical details behind what end-users are asking for, things are not always as easy as they seem.

For wireless IC manufacturers, the main impact revolves around a single theme. That is, the movement of historically non-standard functions into cell phones (think Wi-Fi/VOIP, Bluetooth) and their impact in the design of the end product and the technology roadmap associated with those to achieve market demand.

The emerging trends, standards, and technological innovations that will affect wireless IC makers in the month ahead revolve around the:

MAC and digital baseband and the ability of those devices to support non-standard functionality, such as MP3. RF and mixed-signal transmit and receive path and the support of higher integration levels to reduce cost/price and form factor while enabling multi-mode and multi-band operations. Silicon technology requirements to support higher integration levels without jeopardizing lower power consumption. There''s no doubt that the goal is a single-chip CMOS solution that''s compatible with all standards and is capable of adapting itself. If this is the ultimate end-goal, we must first determine the signs indicating that we are on the right path.

CMOS technology''s full potential wouldn''t have been recently realized if only standalone radios were fabricated. The co-habitation of RF circuits and noisy digital circuitry on the same die was shown to be possible by proper circuit techniques, special deep nwell isolation structures, and exploitation of the digital substrate noise spectrum structure. In addition, multi-band radios require a large number of passive components that take considerable die area and are non-scaling components. This is currently being cleared as a side effect of creating new transceiver architectures and techniques based in complex RF passive networks and high-performance packaging solutions (or modules).

In addition, CMOS has enabled the technology to reach for higher clock frequencies (reducing the size of the RF passive network). In addition, the higher speeds offer other opportunities to compensate at the circuit level for intrinsic technology drawbacks.

The low-noise amplifier (LNA) was the first key component in which CMOS technology needed to prove it could work. The concern there was that the noise level could become progressively higher with lower geometries in such a way that the device''s gain couldn''t compensate and start to produce a higher noise figure. Fortunately, the device''s transconductance, with typical RF device loading, provides higher gain with CMOS scaling down to compensate for additional noise in the channel. This should improve even more as frequencies go above 10 GHz.

CMOS 1/f noise is a physical drawback that will increase with the introduction of new high-K dielectric material in the gate of future CMOS technology nodes. RF CMOS designers have worked successfully through mitigation procedures such as using PMOS transistors instead of NMOS as the device for oscillators and voltage-controlled oscillators (VCOs); more sophisticated circuit-level approaches are being use for low noise oscillators and VCO designs; fractional-N synthesizer architecture; and dividers at the output of high-frequency oscillators, VCOs, and PLLs.

Smaller CMOS geometries and innovative circuit design have enabled higher Q passive components that can be achieved at higher clock frequencies. Therefore, having a higher frequency capability might actually lead to improved designs, even for radios operating at much lower clock frequencies than the frequency limits for a given CMOS technology.

Sigma-delta analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) have also influenced CMOS RFIC architectures. Deep submicron CMOS technology delivers higher speed and enables large oversampling ratios for both ADC and DAC operation. These ADCs and DACs allow for simplified RF front-ends (zero-IF type architecture) and the use of digital synthesizers in multi-band, multi-protocol radios. They''re basically moving a lot of the required filtering for the narrow band part of the signal to the digital domain because high-speed ADCs support a larger bandwidth to be processed in the receiver. And high-speed DACs allow for offsetting signals for proper channelization prior to sending them to the RF transmitter.

CMOS capabilities demonstrations for RF circuits, advances in on-die isolation structures for integrating radio''s delicate circuits with noisy digital circuitry on the same die, and some entirely novel design methods for complex RF passive networks have proven the validity of CMOS for wireless ICs. In the future, those innovations (that have freed silicon area to host complex digital processing and communication engines) will be the building blocks, that allow the design of future multi-band multi-protocol CMOS radios. These wireless IC will have to accommodate various spectra and modulation schemes, each with their own issues for implementation into the end application and at the chip level. This becomes vital in the movement towards a single RF IC, where you can quickly see the issues associated with integration. Currently, techniques are available that are geared to solving this problem, such as software-defined radio (SDR), cognitive radio, and multiple die in a package (system-in-package or SIP).

Only one intrinsic technology problem appeared to be fundamentally unsuited for technology scaling: RF transmission power levels. As CMOS scales, lower voltages are tolerated at the transistor terminals. Circuit-level solutions using power-combining techniques to add the power of parallel power amplifiers (PAs) in CMOS have met with success. The power combination of parallel PAs have being used on-die and on the package. These power-combining circuits became the supporting structure for MIMO or general antenna-diversity/beam-forming-based radios allowing what can be recognized as power combining on air to cope with CMOS RF power transmission limitations.

In RF PAs, moving passives to the package structure will enable the development of full CMOS technology. As CMOS transistors scale, less voltage swing is tolerated at their terminals, and a high-quality impedance converter must be placed between the antenna and the transistors'' drain for high-power transmissions. High-quality impedance converters aren''t available on-die yet and SiGe and GaAs technology appears to be the solution of choice for the next three to four years for modulation schemes with high peak to average power ratio. However, combining digital pre-distortion techniques and outside impedance converters could solve this problem by trading high voltage swing against high current-handling capabilities Such a move is supported by the large pin count capability of flip-chip packages and the more cost-efficient module technology being developed.

At the implementation level, multi-band, multi-protocol radio for always-evolving communication standards is too complex a system to fit in chipset die today, but the previous technology enhancement provides some visibility into what we can expect in the future (see the table).

Note that this discussion doesn''t necessarily preclude advanced RF designs at 2.4 GHz and lower frequencies, but it does highlight the need for RF designers to pay close attention to their design methodology when they move to use more advanced CMOS technology nodes. Not being careful will lead to oscillatory behavior in amplifiers and failure in other active circuits. As multi-band radios are fabricated in the same CMOS process, it''s unlikely that current CMOS modeling will accurately represent the devices'' behavior across such a large frequency span. Because accurate RF/microwave behavior and noise-performance parameters are required, merging VLSI and microwave methods holds more promise. CMOS models plus full disclosure of S-parameter/noise-parameter data and test chips results will mark the new methodology to be followed by CMOS foundries and RFIC CMOS-based manufacturers.

About the author
Gregory A. Quirk is a technology analyst for Semiconductor Insights. He can be reached at .