10/13/2005 11:19 H EDT)
To set these conditions, the circuit is subjected to a programming sequence during its down-time, but only after all start-up and power-on-reset functions are asserted and stabilized. First, a triangular current with a frequency significantly higher than inductor and Gm-C bandwidths RL/L and 1/R2C, respectively, is injected into the inductor-RL network to ensure resistances RL and R2 are negligibly smaller and larger than the inductor and capacitor’s impedances, respectively (Figure 2). Consequently, a mostly square waveform appears across the inductor (that is, VL L dIp/dt ), which the gm1/C filter integrates back into a triangle (that is, dVSense/dt Igm1/C),
(5)
The ac portion of VSense is compared against VTune and the counter gradually tunes gm1 until the peak of VSense equals VTune, at which point the filter gain-bandwidth product (that is, gm1/C) is set, setting and storing gm1 to:
(6)
where IPeak is the peak value of the triangular input test current.
Figure 2. Tuning circuit.
.
The end of the tuning cycle marks the onset of the calibration phase, at which point a DC test input current equal to IPeak is injected into the inductor-RL network, as shown in Figure 3. The impedance across inductor L and capacitor C at DC are significantly smaller than RL and larger than R2, respectively. The resulting sense voltage is therefore:
(7)
which is subsequently compared against VTune. Like before, the counter cycles and adjusts R2 until VSense is equal to VTune, setting the DC transimpedance gain (that is, RLgm1R2) of the network, or:
(8)
where the previously set gm1 (Equation. 6) is substituted in. The new relation satisfies the original intent of equating inductor current bandwidth RL/L to filter bandwidth 1/R(sub>2C, and by setting VTune/IPeak to known constant RSense, gm1R2RL is similarly defined to RSense:
(9)
and Equation. 4 is satisfied.
Figure 3. Calibration circuit.