低功耗
· 1.2 V or 1.5 V 核电压
· 支持单电压系统操作
· 在闪存“冻结”模式下功率耗散为 5 μW
· 低功耗主动 FPGA 操作 (from 12 μW)
· Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
· 易于进入和退出 Flash*Freeze 模式（ 1μs 之内）
高性能
· 15 k to 1 Million 系统门
· 达 144 kbits 的真正双端口 SRAM
· 达 300 个用户 I/O
可编程闪存技术
· 130-nm, 7-Layer Metal, Flash-Based CMOS Process
· Live-at-Power-Up (LAPU) Level 0 Support
· Single-Chip Solution
· Retains Programmed Design When Powered Off
系统内可编程 (ISP) 和安全性
· Secure ISP Using On-Chip 128-Bit Advanced
Encryption Standard (AES) Decryption (except ARM ? -
enabled IGLOO? devices) via JTAG (IEEE 1532–
compliant) ?
· FlashLock ? to Secure FPGA Contents
高性能路由层次
· Segmented, Hierarchical Routing and Clock Structure
先进的 I/O
· 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
· 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
· Bank-Selectable I/O Voltages—up to 4 Banks per Chip
· Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X ? , and
LVCMOS 2.5 V / 5.0 V Input
· Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (AGL250 and above)
· I/O Registers on Input, Output, and Enable Paths
· Hot-Swappable and Cold-Sparing I/Os ?
· Programmable Output Slew Rate ? and Drive Strength
· Weak Pull-Up/-Down
· IEEE 1149.1 (JTAG) Boundary Scan Test
· Pin-Compatible Packages across the IGLOO Family
时钟调节电路 (CCC) 和 PLL ?
· Six CCC Blocks, One with an Integrated PLL
· Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
· Wide Input Frequency Range (1.5 MHz up to 250 MHz)
嵌入式存储 ?
· 1 kbit of FlashROM User Nonvolatile Memory
· SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
· True Dual-Port SRAM (except ×18)
IGLOO FPGA 中的 ARM 处理器支持
· M1 IGLOO Devices—Cortex?-M1 Soft Processor
Available with or without Debug