MAX II CPLD 特征一览 |
| Feature |
Description |
Cost-Optimized Architecture |
Altera ® MAX II CPLDs have a new CPLD architecture that breaks through traditional macrocell power, space, and cost limitations. |
Low Power |
MAX II CPLDs offer the lowest dynamic power in the CPLD industry with one-tenth the power of previous MAX CPLDs. |
Unique Features—Available Only in MAX II CPLDs |
MAX II CPLDs offer 8 Kbits of user-accessible flash memory to implement on-chip serial or parallel non-volatile storage. |
Real-Time In-System Programmability (ISP) |
MAX II CPLDs allow you to update the configuration flash memory while the CPLD is in operation. |
I/O Capabilities |
MAX II CPLDs support a variety of single-ended I/O interface standards such as LVTTL, LVCMOS, and PCI. |
Packages Available |
TQFP, 1.0-mm pitch FBGA, and 0.5-mm pitch MBGA. (1) , (2) , (3) |
Parallel Flash Loader |
MAX II CPLDs feature a JTAG block that can configure external non-JTAG-compliant devices such as discrete flash memory devices using the Parallel Flash Loader megafunction. |
Industrial Temperature Support |
MAX II CPLDs support the industrial temperature range, -40°C to + 100°C (junction), required for various industrial and other temperature-sensitive applications. |
Extended Temperature Support |
MAX II CPLDs are offered in the extended temperature range, -40°C to + 125°C (junction), to support automotive and other temperature-sensitive applications. |