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| NS SDALTEVK三速SDI时钟方案 |
| 作者： 时间：2008-09-10 来源:eaw |
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The 3G SDI SerDes evaluation system consists of:
Cyclone III FPGA development board (sold separately by Altera)
National SDI video and clocking daughter card (SDALTEVK)
Comprehensive user manual, schematics, and bill of materials (BOM)
FPGA IP
Nationals daughter card, SDALTEVK, includes synthesizable FPGA source code available in both Verilog and VHDL to maximize flexibility and facilitate IP customization. The daughter card, available as an option, plugs directly into the Altera Cyclone III development board via Alteras high-speed mezzanine connector (HSMC).
The SDALTEVK daughter card contains:
LMH0344 Triple-rate SDI Adaptive Cable Equalizer
LMH0340 Triple-rate SDI Serializer with integrated cable driver
LMH0341 Triple-rate SDI deserializer with reclocked loop through
LMH1981 Multi-Format Video Sync Separator
LMH1982 Multi-Rate Video Clock Generator
DS90CP22 2x2 LVDS Crosspoint Switch
LP3878 Adjustable Low Noise LDO
LM20242 PowerWise Buck Regulator
The SDALTEVK supports a complete 3G-SDI signal path consisting of adaptive cable equalizer (LMH0344), deserializer with reclocked loop through (LMH0341) and serializer with integrated cable driver (LMH0340). A multi-rate sync separator (LMH1981) and clock generator (LMH1982) deliver ultra-low jitter reference clocks to the host FPGA. A 2x2 LVDS crosspoint switch (DS90CP22) acts as a reference clock selector to choose between four separate clocking options:
Recovered clock from LMH0341 deserializer
Genlock from analog reference, LMH1981 sync separator and LMH1982 clock generator
Local clock generation from LMH1982 in free-run mode
External clock via SMA connector
EVK Block Diagram
EVK Connection Diagram
SDALTEVK
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