Altera 10Gb以太网XAUI解决方案

Alteras 10-Gigabit Ethernet XAUI Solution
Altera provides a complete Media Access Controller (MAC) and PHY FPGA-based solution for a variety of chip-to-chip, backplane, and cable applications using the XAUI protocol as the basis. The solution includes FPGAs with integrated transceivers, development kits, intellectual property (IP) from MorethanIP, collateral, and test data. The solution enables simple, fast protocol implementation, which reduces design risk, shortens development times, and allows you to concentrate on the core functions of the system design.

Stratix II GX devices provide a fully integrated XAUI-compliant solution for high-performance applications, utilizing built-in transceivers to implement the protocol in a single device. Table 1 provides an overview of the Stratix II GX complete XAUI solution.



Technology Background

Altera’s Stratix II GX and Stratix GX devices are equipped with built-in transceivers that provide a dedicated mode for implementing the XAUI interface and allow the integration of multiple PHYs and MACs into a single FPGA. Embedded within the transceivers are dedicated rate-matching FIFO buffers, 8B/10B encoding and decoding functions, and word-alignment functions, all controlled by dedicated XAUI state machines. Each group of four channels also has built-in channel alignment circuitry to minimize skew across the interface. Figure 1 shows the 10-Gigabit Ethernet MAC with integrated PCS block diagram.

Figure 1. 10-Gigabit Ethernet MAC With Integrated PCS Block Diagram



Notes:

1.SPI = serial peripheral interface
2.SFP = small form-factor pluggable
3.MDIO = optional management data interface

The Stratix II GX transceiver module meets all IEEE 802.3ae specifications including jitter generation under 0.35 unit interval (UI) without pre-emphasis and jitter tolerance of more than 0.60 UI, peak-to-peak total. The transceiver module matches the 802.3 sinusoidal jitter-tolerance mask requirement. The 3.125-Gbps x4 channel unidirectional data transfer rate for 10-Gigabit Ethernet complies with the IEEE 802.3ae XAUI definitions for linking physical-layer devices with upper-layer devices. Each transceiver module has 180-mW per channel power dissipation, including receiver, transceiver, clock data recovery (CDR), bias circuit and phase-locked loop (PLL), and maximum pre-emphasis.

The XAUI transceiver module provides a 156-MHz input reference clock and parallel interface along with 4-channel CDR receiver and 4-channel transceiver arrays, an AC-coupled differential interface, and differential PCML at 1.2 V and 1.5 V. The transceiver module also incorporates 1:16 serialization-deserialization (SERDES) with a 16:20 gearbox, 8B/10B coding and lane alignment. The transceivers offer up to 500 percent pre-emphasis and up to 17 dB equalization to compensate high-frequency losses.

Altera offers an array of silicon-proven 10-Gigabit MAC cores with built-in support for the XGMII, XAUI, XSBI (64B/66B PCS layer) interfaces, and OC-192. Built-in support is also provided for flow control, MII management, address-based filtering, and statistics counters for RMON and SNMP. The 10-Gigabit Ethernet MAC layer and reconciliation sub-layer core is compliant with the IEEE 802.3ae specification and supports multiple custom switch fabric enhancements to interface Alteras Stratix II GX devices directly to several 10-Gigabit Ethernet switch devices.

Altera is the first FPGA vendor delivering a multi-gigabit and 10-Gigabit Ethernet PCI Express host adapter card development kit. The host bus adapter, called the Stratix II GX PCI Express Development Kit, is built with Alteras Stratix II GX EP2SGX90 and EP2SGX130 FPGAs, with up to 20 multi-gigabit transceivers accelerating the convergence of network and storage applications using 10-Gigabit Ethernet technology.

Ethernet is by far the most popular local area network (LAN) technology. It is the dominant wired networking protocol. It has evolved from a 1-MHz shared medium signal running on coaxial cable to the present availability of numerous variants operating as fast as 10 Gbps. 10-Gigabit Ethernet provides top-of-the-line performance for leading-edge network development.

PCI Express Development Kit, Stratix II GX Edition

from Altera Corporation

Alteras PCI Express Development Kit, Stratix® II GX Edition delivers a complete PCI Express-based development platform for design engineers. This PCI Express solution, interoperable with industry-standard PCI Express platforms, facilitates the development of custom PCI Express applications. The board also enables system-level solutions by operating as a stand-alone development platform allowing for a variety of custom applications running on the Stratix II GX FPGA. The Development Kit complies with the European Restriction of Hazardous Substances (RoHS) directives.



Development Kit Key Features
Complete Out-of-the-Box PCI Express Experience
PCI-SIG-compliant FPGA, intellectual property (IP) core, board
Stratix II GX FPGA
x1, x4, x8 PCI Express IP MegaCore using OpenCore Plus
One year license for Quartus® II design software
Board schematics and layout information
Reference design and supporting documentation
Modular and Scalable Design
Altera high-speed mezzanine connectors (HSMCs) allow for expansion
Six embedded transceiver channels (1 Gbps–6.375 Gbps), 82 user I/O (41 LVDS pairs)
Two small form pluggable (SFP) module interfaces, with two embedded transceiver channels
(1 Gbps–6.375 Gbps) available
Sufficient logic elements (LEs) and internal RAM to support designs from prototype to production
On-Board Memory
256-Mbyte DDR2 SDRAM, 72 bits, 333 MHz/667 Mbps (Contact your Altera Sales Representative to join Alteras 333-MHz DDR2 support program)
2-Mbyte QDR2 SRAM, 36 bits, 300 MHz/1,200 Mbps
RoHS Compliant
oard, FPGA, and accessories compliant with RoHS directives
Ordering Information
Table 1 provides the ordering information for the PCI Express Development Kit, Stratix II GX Edition.

1 Development Kit Contents
The PCI Express Development Kit, Stratix II GX Edition includes:
Stratix II GX development board (see Figure 1)
Stratix II GX EP2SGX90F1508C3 FPGA
Two Altera HSMCs (daughtercard connectors)
10/100/1000 Ethernet PHY (GMII) with RJ-45 (copper) connector
Two SFP module interfaces (optics not included)
256-Mbyte DDR2 SDRAM (72 bit, 667 Mbps)
2-Mbyte QDR2 SRAM (36 bit, 1,200 Mbps)
64-Mbyte Flash
PCI Express Development Kit, Stratix II GX Edition CD ROM
PCI Express reference design
Complete documentation
Development Kit, Stratix II GX Edition Getting Started User Guide
Board reference manual
Board schematic and layout information
MegaCore IP Library CD
Including the PCI Express, DDR2, and QDR2 IP cores
Quartus II design software
One-year license
Windows platform only
Cable and accessories
USB-BlasterTM download cable
External AC adapter power supply
Power cord (including support for UK, Europe)
Jungo WinDriver Development Toolkit
Figure 1 shows the Stratix II GX development board.
Figure 1. Board Diagram of the PCI Express Stratix II GX Development Board



Figure 2 shows the eye diagram for the PCI Express add-in card transmitter path.

Figure 2. Eye Diagram Based on PCI Express Add-In Card Transmitter Path Compliance Requirement