ST STM8S207 8位MCU开发方案

ST公司的8位STM8S207/208系列MCU有32位存储器接口和三级流水线,在24MHz时可达到20MOPS的性能. STM8S把内核的高速高性能和有多种外设的代码效率组合在一起,同是集成了真正的EEPROM,从而简化了仿真,降低了系统成本和开发时间,增加了工业应用和家用电器的性能.本文介绍了STM8S207/208系列MCU的主要性能,方框图,电源连接图, 参考设计电路图以及调试系统方框图.

The STM8S207/208 performance line 8-bit microcontrollers offer from 32 Kbytes up to 128 Kbytes of program memory and integrated true data EEPROM.

All devices of the STM8S207/208 performance line provide the following benefits:
●Reduced system cost
ntegrated true data EEPROM for up to 300 k write/erase cycles
High system integration level with internal clock oscillators, watchdog and brownout reset
●Performance and robustness
20 MIPS at 24 MHz CPU clock frequency
Robust I/O, independent watchdogs with separate clock source
Clock security system
●Short development cycles
Applications scalability across a common family product architecture with compatible pinout, memory map and modular peripherals.
Full documentation and a wide choice of development tools
●Product longevity
Advanced core and peripherals made in a state-of-the art technology
A family of products for applications with 3.0 V to 5.5 V operating supply

STM8S207/208主要特性:
Core
■Max fCPU: up to 24 MHz, 0 wait states @ fCPU≤16 MHz
■Advanced STM8 core with Harvard architecture and 3-stage pipeline
■Extended instruction set
■Max. 20 MIPS @ 24 MHz

Memories
■Program memory: Up to 128 Kbytes Flash; data retention 20 years at 85°C after 10 kcycles
■Data memory: Up to 2 Kbytes true data EEPROM; endurance 300 kcycles
■RAM: Up to 6 Kbytes
Clock, reset and supply management
■3.0 to 5.5 V operating voltage
■Flexible clock control, 4 master clock sources:
Low power crystal resonator oscillator
External clock input
Internal, user-trimmable 16 MHz RC
Internal low power 128 kHz RC
■Clock security system with clock monitor
■Power management:
Low power modes (Wait, Active-halt, Halt)
Switch-off peripheral clocks individually
■Permanently active, low consumption poweron and power-down reset
Interrupt management
■Nested interrupt controller with 32 interrupts
■Up to 37 external interrupts on 6 vectors

Timers
■2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM)
■Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
■8-bit basic timer with 8-bit prescaler
■Auto wake-up timer
■Window watchdog and independent watchdog
Communications interfaces
■High speed 1 Mbit/s active CAN 2.0B interface
■USART with clock output for synchronous operation - LIN master mode
■LINUART LIN 2.1 compliant, master/slave modes with automatic resynchronization
■SPI interface up to 10 Mbit/s
■I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
■10-bit, ±1 LSB ADC with up to 16 channels
I/Os
■Up to 68 I/Os on an 80-pin package including
11 high sink outputs
■Highly robust I/O design, immune against current injection
■Development support
Hardware Single Wire Interface Module (SWIM) for fast on-chip programming and non intrusive debugging
On-chip Debug Module (DM)



图1. STM8S207/208方框图
The device can be supplied through a 3.0 V to 5.5 V external source. An on-chip power
management system provides the 1.8 V digital supply to the core logic, both in normal and
low power modes. It is also capable of detecting voltage drops, on both main external (3.3
V/5 V) and internal (1.8 V) supplies.
The device provides:
● One pair of pads VDD/VSS (3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to the main regulator
ballast transistor supply.
● Two pairs of pads dedicated for VDD_IO/VSS_IO (3.3 V ± 0.3 V to 5 V ± 0.5 V), which are used to power only the I/O’s. On 32-pin packages, only one pair is bonded.

The device can be supplied through a 3.0 V to 5.5 V external source. An on-chip power
management system provides the 1.8 V digital supply to the core logic, both in normal and
low power modes. It is also capable of detecting voltage drops, on both main external (3.3
V/5 V) and internal (1.8 V) supplies.
The device provides:
● One pair of pads VDD/VSS (3.3 V ± 0.3 V to 5 V ± 0.5 V) dedicated to the main regulator
ballast transistor supply.
● Two pairs of pads dedicated for VDD_IO/VSS_IO (3.3 V ± 0.3 V to 5 V ± 0.5 V), which are used to power only the I/O’s. On 32-pin packages, only one pair is bonded.



The capacitors must be connected as close as possible to the device supplies (especially
VDD in case of dedicated ground plane).Placing a crystal/resonator on OSCIN/OSCOUT is optional. The resonator must be connected as close as possible to the OSCIN and OSCOUT pins. The loading capacitance ground must be connected as close as possible to VSS.
图2.STM8S电源连接图



图3.STM8S参考设计电路图



图4.STM8S调试系统方框图