Xilinx Virtex-5 ML555开发方案

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Xilinx Virtex-5 ML555开发方案

作者：时间：2008-07-10 10:20 来源：eaw

Xilinx公司的 Virtex-5系列采用第二代的ASMBL的柱形架构,包括有四个不同的平台,以及许多硬IP系统级区块,是FPGA市场上有最新功能最强大的特性.本文主要介绍了Virtex-5系列的主要特性,以及用于PCI Express, PCI-X和PCI接口的Virtex-5 LXT ML555 FPGA 开发套件ML555的主要特性,外形图,方框图和ML555详细电路图.

The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains four distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.

Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express™ compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities. The Virtex-5 LXT, SXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability.

Summary of Virtex-5 Features
Four platforms LX, LXT, SXT, and FXT
Virtex-5 LX: High-performance general logic applications
Virtex-5 LXT: High-performance logic with advanced serial connectivity
Virtex-5 SXT: High-performance signal processing applications with advanced serial connectivity
Virtex-5 FXT: High-performance embedded systems with advanced serial connectivity
Cross-platform compatibility
LXT, SXT, and FXT devices are footprint compatible in the same package using adjustable voltage regulators
Most advanced, high-performance, optimal-utilization, FPGA fabric
Real 6-input look-up table (LUT) technology
Dual 5-LUT option
Improved reduced-hop routing
64-bit distributed RAM option
SRL32/Dual SRL16 option
Powerful clock management tile (CMT) clocking
Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting
PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division
36-Kbit block RAM/FIFOs
True dual-port RAM blocks
Enhanced optional programmable FIFO logic
Programmable
True dual-port widths up to x36
Simple dual-port widths up to x72
Built-in optional error-correction circuitry
Optionally program each block as two independent 18-Kbit blocks
High-performance parallel SelectIO technology
1.2 to 3.3V I/O Operation
Source-synchronous interfacing using ChipSync™ technology
Digitally-controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support
Advanced DSP48E slices
25 x 18, two’s complement, multiplication
Optional adder, subtracter, and accumulator
Optional pipelining
Optional bitwise logical functionality
Dedicated cascade connections
Flexible configuration options
SPI and Parallel FLASH interface
Multi-bitstream support with dedicated fallback reconfiguration logic
Auto bus width detection capability
System Monitoring capability on all devices
On-chip/Off-chip thermal monitoring
On-chip/Off-chip power supply monitoring
JTAG access to all monitored quantities
Integrated Endpoint blocks for PCI Express
LXT, SXT, and FXT Platforms
Compliant with the PCI Express Base Specification 1.1
x1, x4, or x8 lane support per block
Works in conjunction with RocketIO™ transceivers
Tri-mode 10/100/1000 Mb/s Ethernet MACs
LXT, SXT, and FXT Platforms
RocketIO transceivers can be used as PHY or connect to external PHY using many soft MII (Media Independent Interface) options
RocketIO™ GTP transceivers 100 Mb/s to 3.75 Gb/s
LXT and SXT Platforms
RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
FXT Platform only
PowerPC 440 Microprocessors
FXT Platform only
RISC architecture
7-stage pipeline
32-Kbyte instruction and data caches included
Optimized processor interface structure (crossbar)
65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard or Pb-free package options
用于PCI Express, PCI-X和PCI接口的Virtex-5 LXT ML555 FPGA 开发套件ML555
This Virtex-5 FPGA based kit provides a development platform for designing and
verifying PCI and PCI-X™ applications utilizing Xilinx LogiCORE™ intellectual property
(IP) cores in a 3.3V signaling environment. The ML555 board is intended to plug-in to a
3.3V keyed system board. The ML555 board is not a Universal add-in card nor is it
intended to plug into a 5V keyed system board.
To develop parallel Peripheral Component Interconnect (PCI™) bus and serial PCI
Express® bus add-in card applications, the Virtex™-5 FPGA ML555 board is configured
and then plugged into a parallel PCI bus system unit or a serial PCI Express system unit.
The board supports 32-bit or 64-bit PCI bus datapaths. The ML555 board has an eight-lane connector that allows the board to be plugged into an eight-lane add-in card socket for PCI Express operation. The ML555 kit does not include a lane conversion adapter, which would allow the eight-lane ML555 board to plug into an add-in card socket for single-lane PCI Express operation.
The ML555 board includes the following:
XC5VLX50T-FFG1136C -1 speed grade FPGA
200-pin 1.8V SODIMM socket with 256 MB (32M x 64 bit) DDR2 SDRAM SODIMM
Three on-board clock sources, two differential SMA clock inputs, and two programmable clock synthesizers:
30 MHz LVCMOS
125 and 200 MHz Epson 2.5V EG-2121CA LVDS and LVPECL, respectively
One Universal Serial Bus (USB) 2.0 port (USB interface cable not provided)
Support for up to four FPGA design images in two Xilinx XCF32P-FSG48C Platform
Flash configuration PROM devices
Static or dynamic device reconfiguration support with the XC2C32 CoolRunner™ II
CPLD
64-bit 3.3V system board keyed connector for PCI or PCI-X operation
Support for Endpoint designs in x1, x4, and x8 lane configurations
Two Small Form-factor Pluggable (SFP) Transceiver module ports (SFP modules are
not included)
Xilinx Generic Interface (XGI) headers support installation of Xilinx Ethernet PHY
daughtercard (sold separately) for 10/100/1000 Mb Ethernet connectivity
Two SAMTEC LVDS interface connectors with up to 24 high-speed LVDS channels
each (cables sold separately)
One Serial ATA (SATA) disk drive interface connector (SATA cable not provided)
One set of SMA ports for offboard GTP transceiver connectivity
User pushbutton switches and LEDs
Device configuration through on-board Platform Flash or Xilinx Platform Cable USB
PCI clocking support for global and regional clocking applications
On-board power regulators (3.0V PCI, 2.5V, 1.8V, 1.0V, 0.9V VTT)
Two programmable clock synthesizer chips to support DDR2 memory interfaces,
10/100/1000 Mb Ethernet protocols, SATA, Fibre Channel, Aurora, and other serial
GTP baud rates.