NS DS90UR241 SERDES方案

NS公司的DS90UR241/124芯片组是5-43MHz DC平衡的24位LVDS串行化器/并行化器,具有24:1和1:24的数据传输,具有用户定义的预加重,支持AC耦合的数据传输,嵌入了时钟和数据恢复(CDR),电源电压3.3V ± 10%,具有广泛的用途.本文介绍了DS90UR241/124芯片组的主要特性, 方框图, DS90UR241和DS90UR124的典型应用电路, 典型的SERDES系统方框图以及串行化器(Tx) PCB电路图与并行化器(Rx) PCB电路图.

DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90UR241/124 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK.

DS90UR241/124主要特性:
5 MHz–43 MHz embedded clock and DC-Balanced 24:1 and 1:24 data transmission
User defined pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable
User selectable clock edge for parallel data on both Transmitter and Receiver
Supports AC-coupling data transmission
Individual power-down controls for both Transmitter and Receiver
Embedded clock CDR (Clock and Data Recovery) on Receiver and no source of reference clock required
All codes RDL (random data lock) to support livepluggable applications
LOCK output flag to ensure data integrity at Receiver side
Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side
Adjustable PTO (progressive turn-on) LVCMOS outputs on Receiver to minimize EMI and SSO effects
@Speed BIST to validate LVDS transmission path
All LVCMOS inputs and control pins have internal pulldown
On-chip filters for PLLs on Transmitter and Receiver
48-pin TQFP package for Transmitter and 64-pin TQFP package for Receiver
Pure CMOS .35 μm process
Power supply range 3.3V ± 10%
Temperature range –40°C to +105°C
Greater than 8 kV HBM ESD structure
Meets ISO 10605 ESD and AEC-Q100 compliance
Backward compatible mode with DS90C241/DS90C124



图1.DS90UR241/124方框图



图2.DS90UR241典型应用电路图



图3.DS90UR124典型应用电路图

NS SERDES评估板
National Semiconductor’s SERDES evaluation kit contains one (1) DS90UR241
Serializer (Tx) board, one (1) DS90UR124 De-serializer (Rx) board, and one (1) generic
two (2) meter USB 2.0 Hi-SPEED cable assembly. National is not recommending using
the USB 2.0 Hi-SPEED cable assembly but is provided in this kit as a generic solution
to show the robustness of the chipset.
Contents of the Evaluation Kit:
1) One Serializer board with the DS90UR241
2) One De-serializer board with the DS90UR124
3) One 2-meter USB 2.0 Hi-SPEED cable assembly
4) Evaluation Kit Documentation (this manual)
5) DS90UR241/124 Datasheet



图4.典型的SERDES应用(18位RGB色彩)



图5.典型的SERDES系统方框图
串行化器(Tx) PCB电路图:



图6.串行器(Tx) PCB电路图(1)



图7.串行器(Tx) PCB电路图(2)



图8.串行器(Tx) PCB电路图(3)
并行化器(Rx) PCB电路图:



图9.并行器(Rx) PCB电路图(1)



图10.并行器(Rx) PCB电路图(2)



图11.并行器(Rx) PCB电路图(3)