Summary
By Gabriel A. Rincón-Mora, Senior Member, IEEE, and H. Pooya Forghani-zadeh, Student Member, IEEE; Georgia Tech Analog and Power IC Design Lab In spite of self-learning, bias-induced and trimming accuracy errors still exist in the system. Current density and temperature settings, for instance, change from the self-learning sequence to the normal operating mode (the test current is for the most part smaller than the load current because of power and associated on-board real-estate concerns). These errors can be adjusted empirically, but not exactly. A first-order temperature dependence, for example, can be superimposed onto RSense. The input-referred offset and linearity of the transconductor across its wide input-common mode range (ICMR) will also impose errors. A linear, low offset transconductor with wide ICMR limits is therefore required. Nevertheless, a PCB prototype implementation of the technique presented exhibited overall full-load DC and AC gain errors of less than 2.3% and 5%, respectively, which is significantly better than previously reported lossless techniques [7]. A complete on-chip prototype is currently under development [8].
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