Microchip公司的PIC24H系列16位MCU包括有The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04以及PIC24HJ128GPX02/X04,采用16位带有增强指令集和寻址模式的改进型哈佛架构,CPU有24位指令,程序计数器(PC)是23位宽,地址高达4Mx24位,广泛用于传感器信号捕获和处理,语音译码和播放以及OLED显示器的控制.本文介绍了PIC24H系列16位MCU的主要特性,方框图和CPU内核方框图以及PIC24H MPLAB® 入门开发套件的方框图,调试方框图和所用元件表,详细电路图包括处理器电路图, 加速度计电路图, 扬声器电路图, 差分放大器和低通滤波器电路图, OLED显示器电路图,开发测试点电路图和USB接口/目标电源开关与调试输入和控制电路图.

PIC24H High-Performance, 16-bit Microcontrollers

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle,
with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point.
The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 devices have sixteen, 16-bit working registers in the programmer.s model.

Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported,allowing A + B = C operations to be executed in a single cycle.

主要特性:

Operating Range:
Up to 40 MIPS operation (at 3.0-3.6V):
-Industrial temperature range (-40℃ to +85℃)
-Extended temperature range (-40℃ to +125℃)
High-Performance CPU:
Modified Harvard architecture
C compiler optimized instruction set
16-bit wide data path
24-bit wide instructions
Linear program memory addressing up to 4M instruction words
Linear data memory addressing up to 64 Kbytes
71 base instructions: mostly 1 word/1 cycle
Flexible and powerful addressing modes
Software stack
16 x 16 multiply operations
32/16 and 16/16 divide operations
Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
8-channel hardware DMA
Up to 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data
transferred via DMA:
Allows data transfer between RAM and a peripheral while CPU is executing code (no
cycle stealing)
Most peripherals support DMA
On-Chip Flash and SRAM:
Flash program memory (up to 128 Kbytes)
Data SRAM (up to 8 Kbytes)
Boot, Secure, and General Security for program Flash
Timers/Capture/Compare/PWM:
Timer/Counters, up to five 16-bit timers:
Can pair up to make two 32-bit timers
One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator
Programmable prescaler
Input Capture (up to four channels):
Capture on up, down or both edges
16-bit capture input functions
4-deep FIFO on each capture
Output Compare (up to four channels):
Single or Dual 16-bit Compare mode
16-bit Glitchless PWM mode
Hardware Real-Time Clock/Calendar (RTCC):
Provides clock, calendar, and alarm functions
Interrupt Controller:
5-cycle latency
118 interrupt vectors
Up to 45 available interrupt sources
Up to three external interrupts
Seven programmable priority levels
Five processor exceptions
Digital I/O:
Peripheral pin Select functionality
Up to 35 programmable digital I/O pins
Wake-up/Interrupt-on-Change for up to 21 pins
Output pins can drive from 3.0V to 3.6V
Up to 5V output with open drain configuration
All digital input pins are 5V tolerant
4 mA sink on all I/O pins
Communication Modules:
4-wire SPI (up to two modules):
Framing supports I/O interface to simple codecs
Supports 8-bit and 16-bit data
Supports all serial clock formats and sampling modes
I2C.:
Full Multi-Master Slave mode support
7-bit and 10-bit addressing
Bus collision detection and arbitration
Integrated signal conditioning
Slave address masking
UART (up to two modules):
Interrupt on address bit detect
Interrupt on UART error
Wake-up on Start bit from Sleep mode
4-character TX and RX FIFO buffers
LIN bus support
IrDA encoding and decoding in hardware
High-Speed Baud mode
Hardware Flow Control with CTS and RTS
Enhanced CAN (ECAN. module) 2.0B active:
Up to eight transmit and up to 32 receive buffers
16 receive filters and three masks
Loopback, Listen Only and Listen All
Messages modes for diagnostics and bus monitoring
Wake-up on CAN message
Automatic processing of Remote
Transmission Requests
FIFO mode using DMA
DeviceNet. addressing support
Parallel Master Slave Port (PMP/EPSP):
Supports 8-bit or 16-bit data
Supports 16 address lines
Programmable Cyclic Redundancy Check (CRC):
Programmable bit length for the CRC generator polynomial (up to 16-bit length)
8-deep, 16-bit or 16-deep, 8-bit FIFO for data input
System Management:
Flexible clock options:
External, crystal, resonator, internal RC
Fully integrated Phase-Locked Loop (PLL)
Extremely low jitter PLL
Power-up Timer
Oscillator Start-up Timer/Stabilizer
Watchdog Timer with its own RC oscillator
Fail-Safe Clock Monitor
Reset by multiple sources
Power Management:
On-chip 2.5V voltage regulator
Switch between clock sources in real time
Idle, Sleep, and Doze modes with fast wake-up
Analog-to-Digital Converters (ADCs):
10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
Two and four simultaneous samples (10-bit ADC)
Up to 13 input channels with auto-scanning
Conversion start can be manual or synchronized with one of four trigger sources
Conversion possible in Sleep mode
±2 LSb max integral nonlinearity
±1 LSb max differential nonlinearity
Comparator Module:
Two analog comparators with programmable input/output configuration
CMOS Flash Technology:
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial and Extended temperature
Low power consumption
Packaging:
28-pin SDIP/SOIC/QFN-S
44-pin TQFP/QFN



图1.PIC24H系列方框图



图2.PIC24H系列CPU内核方框图

PIC24H MPLAB® Starter入门开发套件

This kit is intended to introduce and demonstrate the features of the starter kit and the strong processing capabilities of PIC24H MCU devices. The starter kit demonstrates a low-cost hardware and software solution for processing sensor signals and interfacing audio and visual displays. The board also includes signal conditioning circuitry, which helps users to perform a quick evaluation of the power of PIC24H MCUs by processing signals coming from an external sensor. In addition, the starter kit has on-board debug circuitry you can use to develop and debug your own applications without using other debug tools (i.e., in-circuit emulator or debugger).



图3.PIC24H MPLAB® 入门开发套件方框图



图4.PIC24H MPLAB® 入门开发套件调试方框图

表1. PIC24H MPLAB®入门开发套件元件表:



STARTER KIT HARDWARE COMPONENT DESCRIPTIONS



图5.处理器电路图



图6.加速度计电路图



图7.扬声器电路图



图8.差分放大器和低通滤波器电路图



图9.OLED显示器电路图



图10.用户开关和测试点电路图



图11.USB接口/目标电源开关与调试输入和控制电路图(1)



图12.USB接口/目标电源开关与调试输入和控制电路图(2)