Lattice汽车电子多媒体系统解决方案

本文介绍了Lattice汽车电子多媒体系统解决方案以及所采用的主要元器件, LatticeECP2/M FPGA,标准时钟系列ispClock 以及功率管理器件ispPacPOWR1014A.,本文还介绍了它们的主要性能,方框图以及LatticeECP2/M FPGA评估板的主要性能.



图1.Lattice汽车电子多媒体系统解决方案方框图.
所采用的主要器件:
LatticeECP2/M FPGA
ispClock
ispPacPOWR1014A

一. LatticeECP2 and LatticeECP2M

The LatticeECP2™ and LatticeECP2M™ families redefine the low-cost FPGA category, with more of the best FPGA features for less. By integrating features and capabilities previously only available on higher cost / high performance FPGAs, these families expand the range of applications that can take advantage of low cost FPGAs.

主要性能:

Optimized FPGA Architecture for Low Cost Applications
Feature set optimized for high-volume, low-cost applications
Low cost TQFP, PQFP and BGA packaging
Up to 5.3Mbit Block RAM on LatticeECP2M and 1.1Mbit on LatticeECP2
3.125Gbps Embedded SERDES (ECP2M only)
Low 100mW power per channel
Supports PCIexpress, Ethernet (1GbE and SGMII) plus multiple other tandards
sysDSP Block
High performance multiply, addition, subtract and accumulate
Support widths of up to 36x36
Pre-Engineered Source Synchronous I/O
Simplifies implementation of interfaces such as DDR1/2, SPI4.2 and general purpose ADCs
Supports DDR1/2 at 533Mbps, SPI4.2 at 750Mbps and generic interfaces up to 840Mbps
Enhanced Configuration Options
Configure from SPI, JTAG or microprocessor interfaces
Bitstream encryption (S-Series Only) and dual boot support
TransFR I/O for simple field upgrades
ispLeverCORE Intellectual Property
Speed up your design cycle with ispLeverCORE Intellectual Property
ispLEVER Design Tools
Easy to use SW package supports all Lattice FPGA and programmable logic devices
Evaluation boards available to test your FPGA designs
LatticeECP2/M Applications
LatticeECP2/M devices are ideal for a variety of applications in cost sensitive markets such as Consumer, Automotive, Medical & Industrial, Networking and Computing
LatticeECP2和LatticeECP2M细性能请见:

LatticeECP2/M数据表(pdf)

点此查看全文

LatticeECP2/M 评估板
Lattice has developed four evaluation boards for LatticeECP2/M devices.

LatticeECP2 Standard Evaluation Board:  This board is an efficient design that will help you quickly evaluate the LatticeECP2 FPGA on a ready-made platform. It features an LFE2-50E-6F484C FPGA Device (ECP2-50 in a 484fpBGA package), 64-bit PCI/PCI-x edge connector and form-factor, RS-232 connector, On-board Flash configuration memory, Various LEDs, switches, connectors, headers, an on-board power supply and prototype area.

LatticeECP2 Advanced Evaluation Board: This board features more advanced interfaces for system-level evaluation and development. The board includes a LFE2-50E-6F672C FPGA Device (ECP2-50 in a 672fpBGA package), Dual DDR2 SODIMM memory sockets, 10/100/1G Ethernet PHY with RJ-45 interface, SPI4.2 Tx/Rx connectors (840Mbps), along with many of the features included on the ECP2 Standard Evaluation board.
LatticeECP2M PCI Express x4 Evaluation Board: This board provides a plug in card that can be used to evaluate the LatticeECP2M-50 (or LatticeECP2M-35) in PCI Express and generic SERDES applications.  It provides a PCI Express X4 connector, configuration memory, power supplies, DDR SRAM, a sockatable oscillator, various LEDs and switch inputs.  Demonstration driver software, an evaluation version of the ispLeverCORE PCIexpress IP core and supplied backend logic can be used to quickly evaluation this board in a PC environment.

LatticeECP2M SERDES Evaluation Board: This board can be used to evaluate the SERDES I/O of the LatticeECP2M-50 (or LatticeECP2M-35), interface to PCI Express x1, connect to SERDES via SFP or SATA, or for general SERDES applications.  It includes SMA connectors to 4 quad-channel SERDES, a sockatable oscillator, various LEDs and switch inputs.

The LatticeECP2 Standard Evaluation Board provides a stable yet flexible platform designed to help the user quickly evaluate the performance of the LatticeECP2 FPGA or aid in development of custom designs.

Each LatticeECP2 Standard Evaluation Board includes the following:
LatticeECP2 Standard Evaluation Board featuring
LFE2-50E-6F484C FPGA Device
64-bit PCI/PCI-x edge connector and form-factor
RS-232 connector
Compact Flash Card connector
On-board Flash configuration memory
Prototype area
Various LEDs, switches, connectors, headers, and on-board power supply



图2.LatticeECP2 标准评估板外形图.
二.ispClock– 标准时钟解决方案

Imagine designing your clock nets without using an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts! The answer is Lattice’s revolutionary ispClock5600A family for complex clock nets and ispClock5300S family for simple clock nets. Lattice’s ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements – all while meeting stringent skew and jitter standards!

The ispClock architecture is built around a high performance PLL with programmable input, feedback, and output circuitry providing the flexibility to generate up to five different clock frequencies and route them to any of the output pins. The reference input, feedback input and all outputs can be programmed independently to interface with different I/O standards. Each output’s skew can be individually and precisely controlled to compensate for differences in board trace lengths or timing requirements of the receiving devices.

In ispClock5600A devices there are four configuration profiles stored on-chip for dynamically altering output frequencies for power savings, test modes and other purposes.

The ispClock5300S supports implementation of zero delay and non-zero delay fanout buffers in a single device.

The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock generators designed for use in high performance communications and computing applications. The ispClock5610A provides up to 10 single-ended or five differential clock outputs, while the ispClock5620A provides up to 20 single-ended or 10 differential clock outputs.



图3.ispClock5600A功能方框图.

主要特性:

8MHz to 400MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak
Up to 20 Programmable Fan-out Buffers
Programmable output standards and individual enable controls
LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL
Programmable output impedance
40 to 70Ω in 5Ω increments
Programmable slew rate
Up to 10 banks with individual VCCO and GND
1.5V, 1.8V, 2.5V, 3.3V
Fully Integrated High-Performance PLL
Programmable lock detect
Multiply and divide ratio controlled by
Input divider (1 to 40)
Feedback divider (1 to 40)
Five output dividers (2 to 80 even multiples)
Programmable on-chip loop filter
Compatible with spread spectrum clocks
Precision Programmable Phase Adjustment (Skew) Per Output
16 settings; minimum step size 156ps
Locked to VCO frequency
Up to +/- 12ns skew range
Coarse and fine adjustment modes
Up to Five Clock Frequency Domains
Flexible Clock Reference and External Feedback Inputs
Programmable input standards
LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, SSTL
Clock A/B selection multiplexer
Feedback A/B selection multiplexer
Programmable termination
All Inputs and Outputs are Hot Socket Compliant
Four User-programmable Profiles Stored in E2CMOS&reg; Memory
Supports both test and multiple operating configurations
Full JTAG Boundary Scan Test In-System Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
100-pin and 48-pin TQFP Packages
Applications
Circuit board common clock generation and distribution
PLL-based frequency generation
High fan-out clock buffer
Zero-delay clock buffer



图4. ispClock 5600A应用方框图.
三. 功率管理II ispPAC-POWR1014/A器件

Lattice’s Power Manager II ispPAC-POWR1014/A is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS&reg; technology. The ispPAC-POWR1014/A integrates many power management functions typically requiring multiple ICs.

Please select a document category from the selection on the left-hand side of this page for more information on ispPAC-POWR1014/A.



图5.ispPAC-POWR1014/A方框图.

主要特性:
Monitor and Control Multiple Power Supplies
Simultaneously monitors up to 10 power supplies
Provides up to 14 output control signals
Programmable digital and analog circuitry
Embedded PLD for Sequence Control
24-macrocell CPLD implements both state machines and combinatorial logic functions
Embedded Programmable Timers
Four independent timers
32μs to 2 second intervals for timing sequences
Analog Input Monitoring
10 independent analog monitor inputs
Two programmable threshold comparators per analog input
Hardware window comparison
10-bit ADC for I2C monitoring (ispPAC-POWR1014A only)
High-Voltage FET Drivers
Power supply ramp up/down control
Programmable current and voltage output
Independently configurable for FET control or digital output
2-Wire (I2C/SMBus&#8482; Compatible) Interface
Comparator status monitor
ADC readout
Direct control of inputs and outputs
Power sequence control
Only available with ispPAC-POWR1014A
3.3V Operation, Wide Supply Range 2.8V to 3.96V
In-system programmable through JTAG
Industrial temperature range: -40°C to +85°C
48-pin TQFP package, lead free option

典型应用:

ispPAC-POWR1014 integrates many traditional discrete ICs, which are used to start up a microprocessor with a CPU_RESET, to monitor for over and under voltage and monitor the health of the of the software execution though a watchdog timer. In addition the POWR1014 also integrates power supply sequencing and positive voltage hot-swap control. Varied functionality requirements of each circuit board can be met through programming.