NS LMK04000低噪音精密时钟方案

NS公司的LMK04000系列是具有级联PLL的低噪音时钟抖动消除器的精密时钟调理器,时钟速率高达1080MHz, 有级联PLL中PLL1的相位检测速率高达40MHz,PLL2的相位检测速率高达100MHz. LMK04000系列具有超低的抖动性能, 12 kHz – 20 MHz的RMS抖动为150fs, 100 Hz – 20 MHz抖动为200fs,时钟输出信号为LVPECL/2VPECL, LVDS和 LVCMOS,可用作在数据转换器的时钟,以及用在无线基础设备,网络设备如SONET,SDH, 或DSLAM,医疗设备,军事/航空航天以及测试测量.本文介绍了LMK04000系列的主要特性,方框图, 应用方框图, 典型应用电路图以及回路滤波器和采用晶体振荡器的参考设计电路.

LMK04000 Family of Precision Clock Conditioners Low-Noise Clock Jitter Cleaner with Cascaded PLLs
The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage  controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.

The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation.
PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1.

The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock.

Each clock output pair consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.

LMK04000主要特性:
■Cascaded PLLatinum PLL Architecture
—PLL1
■Phase detector rate of up to 40 MHz
■Integrated Low-Noise Crystal Oscillator Circuit
■Dual redundant input reference clock with LOS
—PLL2
■Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
■Phase detector rate up to 100 MHz
■Input frequency-doubler
■Integrated Low-Noise VCO
■Ultra-Low RMS Jitter Performance
—150 fs RMS jitter (12 kHz – 20 MHz)
—200 fs RMS jitter (100 Hz – 20 MHz)
■LVPECL/2VPECL, LVDS, and LVCMOS outputs
■Support clock rates up to 1080 MHz
■Default Clock Output (CLKout2) at power up
■Five dedicated channel divider and delay blocks
■Pin compatible family of clocking devices
■Industrial Temperature Range: -40 to 85C
■3.15 V to 3.45 V operation
■Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
LMK04000目标应用:
■Data Converter Clocking
■Wireless Infrastructure
■Networking, SONET/SDH, DSLAM
■Medical
■Military/Aerospace
■Test and Measurement



图1.LMK04000功能方框图



图2.LMK04000应用方框图



图3.LMK04000典型应用电路图



图4.LMK04000回路滤波器



图5.采用晶体振荡器的LMK04000参考设计电路