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NXP TDA19978B四路HDMI接收和均衡方案

作者:  时间:2009-03-24 10:56  来源:eaw
NXP公司的TDA19978B是四路HDMI 1.3a兼容的接收器,它嵌入了EDID存储器和自适应均衡器,从而提高了信号质量,允许使用长达25米的电缆. TDA19978B支持HD TV和PC分辨率如WUXGA等. TDA19978B还包括了PC和TV格式识别系统,HDMI频率可高达235 MHz.因此可广泛用于HDTV,高端TV, YCbCr 或 RGB高速视频数字化仪,家庭影院放大器,DVD纪录仪和背投电视以及等离子与LCD TV.本文介绍了TDA19978B的主要特性, 方框图以及应用方框图.

The TDA19978B is a four input HDMI 1.3a compliant receiver with embedded EDID
memory. The built-in auto-adaptive equalizer improves signal quality and allows the use of
cable lengths up to 25 m which are laboratory tested with a 0.5 mm (24 AWG) cable at
2.25 gigasamples per second. In addition, the TDA19978B is delivered with software
drivers to ease configuration and use.
The TDA19978B supports:
TV resolutions:
480i (1440 480i at 60 Hz), 576i (1440 576i at 50 Hz) to HDTV (up to
1920 1080p at 50/60 Hz)
WUXGA (1920 1200p at 60 Hz) reduced blanking format
PC resolutions:
VGA (640 480p at 60 Hz) to UXGA (1600 1200p at 60 Hz)
Deep Color mode in 10-bit and 12-bit:
up to 1920 1080p at 50/60 Hz
WUXGA (1920 1200p at 60 Hz) reduced blanking format
Gamut boundary description
IEC 60958/IEC 61937, OBA (One Bit Audio), DST (Direct Stream Transfer) and HBR
(High Bit Rate) stream
The TDA19978B includes:
An enhanced PC and TV format recognition system
Generation of a 128/256/512 fs system clock allowing the use of simple audio DACs
without an integrated PLL (such as the UDA1334BTS)
An embedded oscillator (an external crystal can also be used)
Improved audio clock generation using an external reference clock
OBA (as used in SACD), DST and HBR stream support
The TDA19978B converts HDMI streams without HDCP into RGB or YCbCr digital
signals. The YCbCr digital output signal can be 4:4:4 or 4:2:2 semi-planar format based
on the ITU-R BT.601 standard or 4:2:2 based on the ITU-R BT.656 format. The device can adjust the output timing of the video port by altering the values of tsu(Q) and th(Q). In
addition, all settings are controllable using the I2C-bus.
TDA19978B主要特性:
Complies with the HDMI 1.3a, DVI 1.0 and CEA-861-D
Four (quad) independent HDMI inputs, up to the HDMI frequency of 235 MHz
Embedded auto-adaptive equalizer on all HDMI links
EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input
Supports color depth processing (8-bit, 10-bit or 12-bit per color)
Color gamut metadata packet with interrupt on each update, readable via the I2C-bus
Up to four S/PDIF or I2S-bus outputs (eight channels) at a sampling rate up to 192 kHz
with IEC 60958/IEC 61937 stream
HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I2S-bus outputs
HBR streams (e.g. DTS-HD master audio and Dolby TrueHD up to eight channels due
to HBR packet for stream with a frame rate up to 768 kHz) support
DSD and DST audio stream up to six DSD channels output for SACD with DST audio
packet support
Channel status decoder supports multi-channel reception
Improved audio clock generation using an external reference clock
System/master clock output (128/256/512 fs) enables the use of the UDA1334BTS
The HDMI interface supports:
All HDTV formats up to 1920 1080p at 50/60 Hz and WUXGA (1920 1200p at
60 Hz) with support for reduced blanking
PC formats up to UXGA (1600 1200p at 60 Hz)
Embedded oscillator (an external crystal can be used)
Frame and field detection for interlaced video signal
Sync timing measurements for format recognition
Improved system for measurements of blanking and video active area allowing an
accurate recognition of PC and TV formats
Repeater capability
Programmable color space input signal conversion from RGB-to-YCbCr or
YCbCr-to-RGB
Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the
ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656
8-bit, 10-bit or 12-bit output formats selectable using the I2C-bus (8-bit and 10-bit only
in 4:4:4 format)
I2C-bus adjustable timing of video port (tsu(Q) and th(Q))
Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode
Internal video and audio pattern generator
Controllable using the I2C-bus; 5 V tolerant and bit rate up to 400 kbit/s
DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s
LV-TTL outputs
Power-down mode
CMOS process
1.8 V and 3.3 V power supplies
Lead-free (Pb) HLQFP144 package
TDA19978B应用:
HDTV
High-end TV
YCbCr or RGB high-speed video digitizer
Home theater amplifier
Projector, plasma and LCD TV
DVD recorder
Rear projection TV
AVR and HDMI splitter



图1.TDA19978B方框图



图2. TDA19978B应用方框图

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