Altera公司的Cyclone III FPGA系列组合了高性能,低功耗和低成本,逻辑单元(LE)从5K到200K,存储器从0.5Mb到8Mb,静态功耗小于1/4瓦,为各种大批量低功耗对成本敏感的应用提供了非常理想的解决方案,广泛应用在汽车电子,消费类电子,显示器,工业,军用,视频和图像处理以及无线通信.本文介绍了Cyclone III FPGA系列的主要特性,以及Arrow公司的采用Cyclone III EP
Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power consumption, Cyclone III device family provides the ideal solution for your high-volume, low-power, and cost-sensitive applications. To address the unique design needs, Cyclone III device family offers the following two variants:
■ Cyclone III: lowest power, high functionality with the lowest cost
■ Cyclone III LS: lowest power FPGAs with security
With densities ranging from 5K to 200K logic elements (LEs) and 0.5 Mbits to 8 Mbits
Cyclone III FPGA主要特性:
Cyclone III Device Family Features
Cyclone III device family offers the following features:
Lowest Power FPGAs
■ Lowest power consumption due to:
■ TSMC low-power process technology
■ Altera® power-aware design flow
■ Low-power operation offers the following benefits:
■ Extended battery life for portable and handheld applications
■ Reduced or eliminated cooling system costs
■ Operation in thermally-challenged environments
■ Hot-socketing operation support
Design Security Feature
Cyclone III LS devices offer the following design security features:
■ Configuration security using advanced encryption standard (AES) with 256-bit volatile key
■ Routing architecture optimized for design separation flow with the Quartus® II software
■ Design separation flow achieves both physical and functional isolation between design partitions
■ Ability to disable external JTAG port
■ Error Detection (ED) Cycle Indicator to core
■ Provides a pass or fail indicator at every ED cycle
■ Provides visibility over intentional or unintentional change of configuration random access memory (CRAM) bits
■ Ability to clear contents of the FPGA logic, CRAM, embedded memory, and AES key
■ Internal oscillator enables system monitor and health check capabilities
Increased System Integration
■ High memory-to-logic and multiplier-to-logic ratio
■ High I/O count, low-and mid-range density devices for user I/O constrained applications
■ Adjustable I/O slew rates to improve signal integrity
■ Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
■ Supports the multi-value on-chip termination (OCT) calibration feature to eliminate variations over process, voltage, and temperature (PVT)
■ Four phase-locked loops (PLLs) per device provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces
■ Five outputs per PLL
■ Cascadable to save I/Os, ease PCB routing, and reduce jitter
■ Dynamically reconfigurable to change phase shift, frequency multiplication or division, or both, and input frequency in the system without reconfiguring the device
■ Remote system upgrade without the aid of an external controller
■ Dedicated cyclical redundancy code checker circuitry to detect single-event upset (SEU) issues
■ Nios® II embedded processor for Cyclone III device family, offering low cost and custom-fit embedded processing solutions
■ Wide collection of pre-built and verified IP cores from Altera and Altera Megafunction Partners Program (AMPP) partners
■ Supports high-speed external memory interfaces such as DDR, DDR2, SDR SDRAM, and QDRII SRAM
■ Auto-calibrating PHY feature eases the timing closure process and eliminates variations with PVT for DDR, DDR2, and QDRII SRAM interfaces Cyclone III device family supports vertical migration that allows you to migrate your device to other devices with the same dedicated pins, configuration pins, and power pins for a given package-across device densities. This allows you to optimize device density and cost as your design evolves.
Cyclone III Device Family Features
低功耗参考平台(LPRP)
The Low Power Reference Platform (LPRP)
Arrow Electronics, Altera Corporation, and Linear Technology have combined industry-leading power management solutions with a low power Cyclone® III FPGA and board-level power management IP in the revolutionary LPRP. Purchasing an LPRP kit enables designers to learn first-hand the latest design techniques for power-sensitive applications, from battery charging to understanding the interaction between device selection, system performance, system power modes, and their combined effect on power consumption. Using the LPRP kit, engineers can implement either an Altera® Nios® II processor or ARM Cortex M1 32-bit embedded processor inside the Cyclone® III FPGA.
The LPRP can be used to demonstrate low power designs provided with the kit or to develop new ones. It features the devices listed below.
图1.低功耗参考平台(LPRP)外形图
图2.低功耗参考平台(LPRP)方框图
图3.低功耗参考平台(LPRP)电路图(1)
图4.低功耗参考平台(LPRP)电路图(2)
图5.低功耗参考平台(LPRP)电路图(3)
图6.低功耗参考平台(LPRP)电路图(4)
图7.低功耗参考平台(LPRP)电路图(5)
图8.低功耗参考平台(LPRP)电路图(6)
图9.低功耗参考平台(LPRP)电路图(7)
图10.低功耗参考平台(LPRP)电路图(8)
图11.低功耗参考平台(LPRP)电路图(9)
图12.低功耗参考平台(LPRP)电路图(10)
图13.低功耗参考平台(LPRP)电路图(11)
图14.低功耗参考平台(LPRP)电路图(12)
图15.低功耗参考平台(LPRP)电路图(13)
图16.低功耗参考平台(LPRP)电路图(14)