图1.MC56F8006/2方框图

MC56F8006主要特性:

High Performance Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard Architecture

• Up to 32 Million Instructions Per Second (MIPS) at 32 MHz core frequency

• 155 Basic Instructions in conjunction with up to 20 address modes

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,real-time debugging

Operation Range

• From power-on-reset: Approximately 1.9 V to 3.6 V

• Operating: 1.8 V to 3.6 V (power supplies and input/output)

• Ambient temperature operating range: -40℃ to 105℃

Memory Configuration

• Up to 16 Kbytes program flash memory with flash security protection

• 2 Kbytes unified program/data RAM

Module Configuration

• One 6-channel PWM module

— Up to 96 MHz PWM operating clock

— 15 bits of resolution

— Center-Aligned and edge-aligned PWM signal mode

— Four programmable fault inputs with programmable digital filter

— Double-Buffered PWM registers

• Dual 12-bit SAR analog-to-digital converters (ADC)

• 3.042 μSec for first ADC conversion, 2.125 μSec for subsequent

• Linear successive approximation algorithm with 12-bit resolution

• Up to 24 analog inputs

• Output formatted in 12-, 10-, or 8-bit right-justified unsigned format

• Single or continuous conversion (automatic return to idle after single conversion)

• Configurable sample time and conversion speed/power

• Conversion complete flag and interrupt

• Input clock selectable from up to four sources

• Operation in wait or stop3 modes for lower noise operation

• Asynchronous clock source for lower noise operation

• Selectable asynchronous hardware conversion trigger

• Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value

• Temperature sensor

• Two differential programmable gain amplifiers (PGA)

— Sampled PGA architecture

— Common mode noise and offset are automatically cancelled out (2–4 consecutive samples required for noise/offset cancellation)

— Sample may be synchronized with PWM operation using the PWM sync output and

programmable delay block

— Sampling time can be precisely controlled (to less than 0.1 μs)

— Several programmable gains (1×, 2×, 4×, 8×, 16×, and 32×)

— 0.14 MSPS maximum

— Selectable tradeoff for slower/low power versus faster/more power

— Rail-to-rail input voltage range

— Single-ended output routed directly to on-chip ADCs

• One high-speed serial communication interface (SCI) with LIN slave functionality

— Max baud rate of 6 Mbps when using 3× IPBus at 96 MHz.

— Full-duplex or single-wire operation

— Two receiver wake-up methods:

– Idle line

– Address mark

• One serial peripheral interface (SPI)

— Full-duplex operation

— Master and slave modes

— Programmable Length Transactions (2 to 16 bits)

• Dual 16-bit general-purpose timers (GPT)

— Up to 96 MHz operating clock

— Eight independent 16-bit counter/timers with cascading capability

— Each timer has capture and compare capability

— Up to 12 operating modes

• One programmable interval timer (PIT)

— 16-bit counter/timer

— Programmable count modulo

• Real-time counter (RTC) which can be used to implement a real-time clock

— 8-Bit up-counter

— Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-Based divider values

– 1 kHz internal oscillator

– External clock

– 32 kHz internal clock

• One programmable delay block (also known as a sync timer) for coordination of the ADC, PGA, or comparator samples with PWM

• One inter-integrated circuit (I2C) port

— Operates up to 400 kbps

— Supports both master and slave operation

— Supports both 10-bit address mode and broadcasting mode

— System Management Bus Specification (SMBus) Version 2 support

• Computer operating properly (COP)/watchdog timer with independent 1 kHz on-chip oscillator

— Integrated 1 KHz oscillator

— Programmable timeout period

— Programmable wait and stop and partial powerdown mode operation

— Choice of clock sources for counter

— Support for switched power modes

• Clock sources

— On-chip 8 Mhz relaxation oscillator

— On-chip 1 Khz clock

— External clock (32 Khz or 8 Mhz): Crystal oscillator, ceramic resonator, and external clock source

• Integrated phase-locked loop (PLL)

• Three on-chip comparators

— Selectable input source from external pins

— Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output

— Programmable output polarity

— Comparator output may be:

– Sampled

– Windowed (ideal for certain PWM zero-crossing-detection applications)

– Digitally Filtered

– Filter can be bypassed

– Clocked via external SAMPLE signal or scaled peripheral clock

• JTAG/Enhanced On-Chip Emulation (EOnCE™) for unobtrusive, real-time debugging

• Up to 40 general-purpose input/output (GPIO) lines

— Programmable output drive level, slew-rate control, and optional input low-pass filters

— Individual control for each pin to be in either Peripheral or GPIO mode

— Individual Input/Output direction control for each pin in GPIO mode

— Individual Pull-Up Enable Control for each input pin in either Peripheral or GPIO mode

— 15 mA sink/source current

Power Management

• On-chip regulator for digital and analog circuitry to lower cost and reduce noise

• Integrated power-on reset

• Low-voltage interrupt with a user-selectable trip voltage of 1.86 or 2.33 V

• User selectable brown-out reset

• RUN, WAIT, and STOP modes

• Low-power RUN, WAIT, and STOP modes

• Partial Power Down mode

— RAM, PMC, and COP remain powered

— Rest of the chip is shut down for extreme power savings

• Each peripheral can be individually disabled to save power

MC56F8006目标应用:

• Motor Control

3 phase BLDC motor control

Entry-level field -oriented control

PMSM control

Large & small home appliances

• Advanced Power Conversion

Board mounted & industrial power supplies

Switched-mode power supply & power management

Arc fault protection

Advance lighting control

• Power-Sensitive Applications

Medical portable diagnostic and Therapeutic devices

Handheld power tools

Instrumentation

MC56F8006演示板

MC56F8006DEMO is a cost-effective board targeting quick digital signal controller (DSC) evaluation, demonstration and debugging of the Freescale MC56F8006VLF digital signal controller

MC56F8006演示板主要特性:

MC56F8006 DSC evaluation board with MC9S08JM60 for USB (and more)

J1 - 40 pin header to access MC56F8006 pins compatible with 56F80xx demos

J2 - 8 pin header for remaining GPIO for 8006

Option to power with jack, USB, or a J1 pin

USB allows any baud rate PC COM port bridge to SCI of MC56F8006

JTAG control and debug of MC56F8006

BDM control and debug of MC9S08JM60

COM port ready for RS232 build out

6 8006 PWM LED indicators

Watch Crystal Reference (Y1) pads for 8006

图2.MC56F8006演示板外形图

图3.MC56F8006演示板电路图(1)

图4.MC56F8006演示板电路图(2)