Freescle MC56F8006 BLDC马达控制方案
作者: 时间:2009-11-11 14:21 来源:
Freescle 公司的MC56F8006//MC56F8002是数字信号控制器(DSC),在单片上集成了DSP的处理功能和微控制器的功能,以及各种外设,以创建非常高性能比的解决方案. MC56F8006//MC56F8002包括多达16KB的程序闪存,2KB 数据/程序RAM,32MHz核频率的性能高达32MIPS,主要应用于工业控制,家用电器,智能传感器,防火和安防系数,开关电源和电源管理,电表,马达控制以及仪器仪表等.本文介绍MC56F8006//MC56F8002主要特性,方框图,内核方框图, 外设子系统方框图, 控制器子板电路图和材料清单.
MC56F8006/MC56F8002 Digital Signal Controller
The 56F8006/56F8002 is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution.
Because of its low cost, configuration flexibility, and compact program code, the 56F8006/56F8002 is well-suited for many applications. The 56F8006/56F8002 includes many peripherals that are especially useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Switched-mode power supply and power management
• Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical device/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.
The 56F8006/56F8002 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8006/56F8002 also offers up to 40 general-purpose input/output (GPIO) lines, depending on peripheral configuration.
The 56F8006/56F8002 digital signal controller includes up to 16 KB of program flash and 2 KB of unified data/program RAM. Program flash memory can be independently bulk erased or erased in small pages of 512 bytes (256 words).
On-chip features include:
• Up to 32 MIPS at 32 MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• On-chip memory
– 56F8006: 16 KB (8K x 16) flash memory
– 56F8002: 12 KB (6K x 16) flash memory
– 2 KB (1K x 16) unified data/program RAM
• One 6-channel PWM module
• Two 28-channel, 12-bit analog-to-digital converters (ADCs)
• Two programmable gain amplifiers (PGA) with gain up to 32x
• Three analog comparators
• One programmable interval timer (PIT)
• One high-speed serial communication interface (SCI) with LIN slave functionality
• One serial peripheral interface (SPI)
• One 16-bit dual timer (2 x 16 bit timers)
• One programmable delay block (PDB)
• One SMBus compatible inter-integrated circuit (I2C) port
• One real time counter (RTC)
• Computer operating properly (COP)/watchdog
• Two on-chip relaxation oscillators — 1 kHz and 8 MHz (400 kHz at standby mode)
• Crystal oscillator
• Integrated power-on reset (POR) and low-voltage interrupt (LVI) module
• JTAG/enhanced on-chip emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 40 GPIO lines
• 28-pin SOIC, 32-pin LQFP, and 48-pin LQFP packages
图1.MC56F8006/MC56F8002 方框图
图2. 56800E核方框图
图3.MC56F8006/MC56F8002 外设子系统方框图
Freescale’s MC56F8006 Controller Daughter Board for BLDC/PMSM Motor Control Drive, together with a 3-phase BLDC/PMSM Motor Control Drive board, create a single unit for developing BLDC/PMSM motor-control applications.
The daughter board is connected via two connectors to the 3-phase BLDC/PMSM Motor Control Drive board. All necessary signals are available to allow a variety of algorithms to control the 3-phase PMSM and BLDC motors.
图4.MC56F8006 控制器子板外形图
图5.MC56F8006 控制器子板连接器和插头电路图
图6.MC56F8006 控制器子板控制器和插头电路图
材料清单: