Silicon Lab Si4703C FM调谐方案

Silicon Lab 公司的Si4702/03C FM收音机调谐器集成了从天线输入到立体声音频输出的全部功能. Si4703-C采用适合于欧洲无线电系统(RDS)和US无线电广播数据系统(RBDS)的数字处理器,包括符号译码所需的所有功能,同步区块,误差检测以及误差修正等,支持世界范围的FM广播频率76–108 MHz. Si4702/03C广泛应用于手机,MP3播放器,手提收音机,USB FM收音机,PDA,笔记本电脑,消费类电子以及手提导航系统.本文介绍了Si4702/03C的详细特性,方框图以及典型应用电路和材料清单(BOM).

BROADCAST FM RADIO TUNER FOR PORTABLE
The Si4702/03 integrates the complete tuner function from antenna input to stereo audio output for FM broadcast radio reception.
The Si4702/03-C19 extends Silicon Laboratories Si4700/01 FM tuner family, and further increases the ease and attractiveness of adding FM radio reception to mobile devices through small size and board area, minimum component count, flexible programmability, and superior, proven performance. Si4702/03-C19 software is backwards compatible to existing Si4700/01 and Si4702/03-B16 FM Tuner designs. The Si4702/03-C19 benefits from proven digital integration and 100% CMOS process technology, resulting in a completely integrated solution. It is the industrys
smallest footprint FM tuner IC requiring only 10 mm2 board space and one external bypass capacitor.
The device offers significant programmability, and caters to the subjective nature of FM listeners and variable FM broadcast environments world-wide through a simplified programming interface and mature functionality.
The Si4703-C incorporates a digital processor for the European Radio Data System (RDS) and the US Radio Broadcast Data System (RBDS) including all required symbol decoding, block synchronization, error detection, and error correction functions. RDS enables data such as station identification and song name to be displayed to the user. The Si4703-C offers a detailed RDS view and a standard view, allowing adopters to selectively choose granularity of RDS status, data, and block errors. Si4703-C software is backwards compatible to the proven Si4701, adopted by leading cell-phone and MP3 manufacturers world-wide.
The Si4702/03-C19 is based on the superior, proven performance of Silicon Laboratories Aero architecture offering unmatched interference rejection and leading sensitivity. The device uses the same programming interface as the Si4701 and supports multiple bus-modes. Power management is also simplified with an integrated regulator allowing direct connection to a 2.7 to 5.5 V battery.
The Si4702/03-C19 device’s high level of integration and complete FM system production testing increases quality to manufacturers, improves device yields, and simplifies device manufacturing and final testing.
FM Receiver
The Si4702/03-C19’s patented digital low-IF architecture reduces external components and
eliminates the need for factory adjustments. The receive (RX) section integrates a low noise amplifier (LNA) supporting the worldwide FM broadcast band (76 to 108 MHz). An automatic gain control (AGC) circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers. For testing purposes, the AGC can be disabled with the AGCD bit. Refer to Section 6. Register Descriptions on page 23 for additional programming and configuration information.
The Si4702/03-C19 architecture and antenna design increases system performance. To ensure proper performance and operation, designers should refer to the guidelines in AN231: Si4700/01/02/03 Headphone and Antenna Interface. Conformance to these guidelines will help to ensure excellent performance even in weak signal or noisy environments.
An image-reject mixer downconverts the RF signal to low-IF. The quadrature mixer output is amplified, filtered, and digitized with high resolution analog-to-digital converters (ADCs). This advanced architecture achieves superior performance by using digital signal processing (DSP) to perform channel selection, FM demodulation, and stereo audio processing compared to traditional analog architectures.
General Purpose I/O Pins
The pins GPIO1–3 can serve multiple functions. GPIO1 and GPIO3 can be used to select between 2-wire and 3-wire modes for the control interface as the device is brought out of reset. See Section “4.9. Reset, Powerup, and Powerdown”. After powerup of the device, the GPIO1–3 pins can be used as general purpose inputs/outputs, and the GPIO2–3 pins can be used as interrupt request pins for the seek/tune or RDS ready functions and as a stereo/mono indicator respectively.
It is recommended that the GPIO2–3 pins not be used as interrupt request outputs until the powerup time has completed (see Section “4.9. Reset, Powerup, and Powerdown”). The GPIO3 pin has an internal, 1 MΩ, ±15% pull-down resistor that is only active while RST is low. General purpose input/output functionality is available regardless of the state of the VA and VD supplies, or the ENABLE and DISABLE bits.
RDS/RBDS Processor and Functionality
The Si4703 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction. RDS functionality is enabled by setting the RDS bit. The device offers two RDS modes, a standard mode and a verbose mode.
The primary difference is increased visibility to RDS block-error levels and synchronization status with verbose mode.
Setting the RDS mode (RDSM) bit low places the device in standard RDS mode (default). The device will set the RDS ready (RDSR) bit for a minimum of 40 ms when a valid RDS group has been received. Setting the RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 01 will configure GPIO2 to pulse low for a minimum of 5 ms when a valid RDS group has been received. If an nvalid
group is received, RDSR will not be set and GPIO2 will not pulse low. In standard mode RDS synchronization (RDSS) and block error rate A, B, C and D (BLERA, BLERB, BLERC, and BLERD) are unused and will read 0. This mode is backward compatible with earlier firmware revisions.
Setting the RDS mode bit high places the device in RDS verbose mode. The device sets RDSS high when synchronized and low when synchronization is lost. If the device is synchronized, RDS ready (RDSR) will be set for a minimum of 40 ms when a RDS group has been received. Setting the RDS interrupt enable (RDSIEN) bit and GPIO2[1:0] = 01 will configure GPIO2 to pulse low for a minimum of 5 ms if the device is synchronized and an RDS group has been received.
BLERA, BLERB, BLERC and BLERD provide block-error levels for the RDS group. The number of bit errors in each block within the group is encoded as follows: 00 = no errors, 01 = one to two errors, 10 = three to five errors, 11 = six or more errors. Six or more errors in a block indicate the block is uncorrectable and should not be used.
Stereo Audio Processing
The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was
developed in 1961 and is used worldwide. Todays MPX signal format consists of left + right (L+R) audio, left –right (L–R) audio, a 19 kHz pilot tone.
The Si4702/03-C19s integrated stereo decoder automatically decodes the MPX signal. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L-R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L-R) signal. Separate left and right channels are obtained by adding and subtracting the (L+R) and (L-R) signals, respectively. The Si4703-C uses frequency information from the 19 kHz stereo pilot to recover the
57 kHz RDS/RBDS signal.
combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. The signal level range over which the stereo to mono blending occurs can be adjusted by setting the BLNDADJ[1:0] register. Stereo/mono status can be monitored with the ST register bit and mono operation can be forced with the MONO register bit.
Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. All FM receivers incorporate a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two time constants, 50 or 75 μs, are used in various regions.
The de-emphasis time constant is programmable with the DE bit. High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins.
The audio output may be muted with the DMUTE bit. Volume can be adjusted digitally with the
VOLUME[3:0] bits. The volume dynamic range can be set to either –28 dBFS (default) or –58 dBFS by setting VOLEXT=1.
The soft mute feature is available to attenuate the audio outputs and minimize audible noise in weak signal conditions. The soft mute attack and decay rate can be adjusted with the SMUTER[1:0] bits where 00 is the fastest setting. The soft mute attenuation level can be
adjusted with the SMUTEA[1:0] bits where 00 is the most attenuated. The soft mute disable (DSMUTE) bit may be set high to disable this feature.
Tuning
The Si4702/03-C19 uses Silicon Laboratories’ patented and proven frequency synthesizer technology including a completely integrated VCO. The frequency synthesizer generates the quadrature local oscillator signal used to downconvert the RF input to a low intermediate frequency. The VCO frequency is locked to the reference clock and adjusted with an automatic
frequency control (AFC) servo loop during reception. The tuning frequency is defined as:
Channel spacing of 50, 100 or 200 kHz is selected with bits SPACE[1:0]. The channel is selected with bits CHAN[9:0]. Band selection for Japan, Japan wideband, or Europe/U.S./Asia is set with BAND[1:0]. The tuning operation begins by setting the TUNE bit. After tuning completes, the seek/tune complete (STC) bit will be set and the RSSI level is available by reading bits RSSI[7:0]. The TUNE bit must be set low after the STC bit is set high in order to complete the tune operation
and clear the STC bit.
Seek tuning searches up or down for a channel with an RSSI greater than or equal to the seek threshold set with the SEEKTH[7:0] bits. In addition, optional SNR and/or impulse noise detector criteria may be used to qualify valid stations. The SKSNR[3:0] bits set the SNR threshold required. The SKCNT[3:0] bits set the impulse noise threshold. Using the extra seek qualifiers can reduce false stops and, in combination with lowering the RSSI seek threshold, increase the number of found stations. The SNR and impulse noise detectors are disabled by default for backwards compatibility.
Two seek modes are available. When the seek mode (SKMODE) bit is low and a seek is initiated, the device seeks through the band, wraps from one band edge to the other, and continues seeking. If the seek operation is unable to find a valid channel, the seek failure/band limit (SF/BL) bit is set high and the device returns to the channel selected before the seek operation began.
When the SKMODE bit is high and a seek is initiated, the device seeks through the band until the band limit is reached and the SF/BL bit is set high. A seek operation is initiated by setting the SEEK and SEEKUP bits. After the seek operation completes, the STC bit is set, and the RSSI level and tuned channel are available by reading bits RSSI[7:0] and bits READCHAN[9:0]. During
a seek operation READCHAN[9:0] is also updated and may be read to determine and report seek progress. The STC bit is set after the seek operation completes.
The channel is valid if the seek operation completes and the SF/BL bit is set low. At other times, such as before a seek operation or after a seek completes and the SF/BL bit is set high, the channel is valid if the AFC Rail (AFCRL) bit is set low and the value of RSSI[7:0] is greater than or equal to SEEKTH[7:0]. Note that if a valid channel is found but the AFCRL bit is set, the audio output is muted as in the softmute case discussed in Section “4.5. Stereo Audio Processing”. The SEEK bit must be set low after the STC bit is set high in order to complete the seek operation. Setting the STC bit low clears STC status and SF/BL bits. The seek operation may be aborted by setting the SEEK bit low at any time.
The device can be configured to generate an interrupt on GPIO2 when a tune or seek operation completes. Setting the seek/tune complete (STCIEN) bit and GPIO2[1:0] = 01 will configure GPIO2 for a 5 ms low interrupt when the STC bit is set by the device.
Reference Clock
The Si4702/03-C19 accepts a 32.768 kHz reference clock to the RCLK pin. The reference clock is required whenever the ENABLE bit is set high. Refer to Table 3, “DC Characteristics1,” on page 5 for input switching voltage levels and Table 8, FM Receiver Characteristics, on page 12 for frequency tolerance information.
An onboard crystal oscillator is available to generate the 32.768 kHz reference when an external crystal and load capacitors are provided. Refer to 2. Typical Application Schematic on page 14. The oscillator must be enabled or disabled while in powerdown (ENABLE = 0) as shown in Figure 9, “Initialization Sequence,” on page 21. Register 07h, bits [13:0], must be preserved as 0x0100
while in powerdown. Note that RCLK voltage levels are not specified. The typical RCLK voltage level, when the crystal oscillator is used, is 0.3 Vpk-pk.
Si4702/03-C19 Internal Crystal Oscillator Errata
The Si4702/03-C19 seek/tune performance may be affected by data activity on the SDIO bus when using the integrated internal oscillator. SDIO activity results from polling the tuner for status or communicating with other devices that share the SDIO bus. If there is SDIO bus activity while the Si4702/03-C19 is performing the seek/tune function, the crystal oscillator may experience
jitter, which may result in mistunes and/or false stops. SDIO activity during all other operational states does not affect performance.
For best seek/tune results, Silicon Laboratories recommends that all SDIO data traffic be suspended during Si4702/03-C19 seek and tune operations. This is achieved by keeping the bus quiet for all other devices on the bus, and delaying tuner polling until the tune or seek operation is complete. The STC (seek/tune complete) interrupt should be used instead of polling to determine when a seek/tune operation is complete.
The layout guidelines in Si4700/01/02/03 Evaluation Board User’s Guide, Section 8.3 Si4702/03-C19 Daughter Card should be followed to help ensure robust FM performance.
Please refer to the posted Si4702/03 Internal Crystal Oscillator Errata for more information.
Control Interface
Two-wire slave-transceiver and three-wire interfaces are provided for the controller IC to read and write the control registers. Refer to “4.9. Reset, Powerup, and Powerdown” for a description of bus mode selection. Registers may be written and read when the VIO supply is applied regardless of the state of the VD or VA supplies. RCLK is not required for proper register operation.
3-Wire Control Interface
For three-wire operation, a transfer begins when the SEN pin is sampled low by the device on a rising SCLK edge. The control word is latched internally on rising SCLK edges and is nine bits in length, comprised of a four bit chip address A7:A4 = 0110b, a read/write bit (write = 0 and read = 1), and a four bit register address, A3:A0. The ordering of the control word is A7:A5, R/W, A4:A0. Refer to Section 5. Register Summary on page 22 for a list of all registers and their addresses.
For write operations, the serial control word is followed by a 16-bit data word and is latched internally on rising SCLK edges.
For read operations, a bus turn-around of half a cycle is followed by a 16-bit data word shifted out on rising SCLK edges and is clocked into the system controller on falling SCLK edges. The transfer ends on the rising SCLK edge after SEN is set high. Note that 26 SCLK cycles are required for a transfer, however, SCLK may run continuously.
For details on timing specifications and diagrams, refer to Table 6, “3-Wire Control Interface Characteristics,” on page 8, Figure 3, “3-Wire Control Interface Write Timing Parameters,” on page 8, and Figure 4, “3-Wire Control Interface Read Timing Parameters,” on page 9.
2-wire Control Interface
For two-wire operation, the SCLK and SDIO pins function in open-drain mode (pull-down only) and must be pulled up by an external device. A transfer begins with the START condition (falling edge of SDIO while SCLK is high). The control word is latched internally on rising SCLK edges and is eight bits in length, comprised of a seven bit device address equal to 0010000b and a read/write bit (write = 0 and read = 1).
The device acknowledges the address by driving SDIO low after the next falling SCLK edge, for 1 cycle. For write operations, the device acknowledge is followed by an eight bit data word latched internally on rising edges of SCLK. The device acknowledges each byte of data written by driving SDIO low after the next falling SCLK edge, for 1 cycle. An internal address counter automatically increments to allow continuous data byte writes, starting with the upper byte of register 02h, followed by the lower byte of register 02h, and onward until the lower byte of the last register is reached. The internal address counter then automatically wraps around to the upper byte of register 00h and proceeds from there until continuous writes end. Data transfer ends with the STOP condition (rising edge of SDIO while SCLK is high). After every STOP condition, the internal address counter is reset.

主要特性:
This data sheet applies to Si4702/03-C Firmware 19 and greater
Worldwide FM band support (76–108 MHz)
Digital low-IF receiver
Frequency synthesizer with integrated VCO
Seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Programmable de-emphasis (50/75 μs)
Adaptive noise suppression
Volume control
Line-level analog output
32.768 kHz reference clock
2-wire and 3-wire control interface
2.7 to 5.5 V supply voltage
Integrated LDO regulator allows direct connection to battery
3 x 3 mm 20-pin QFN package
Pb-free/RoHS compliant
RDS/RBDS Processor (Si4703)
Integrated crystal oscillator

应用:
Cellular handsets
MP3 players
Portable radios
USB FM radio
PDAs
Notebook PCs
Portable navigation
Consumer electronics


图1.Si4702/03C功能方框图



图2. Si4702/03C典型应用电路



表1.典型应用电路中材料清单(BOM)