Calypto推出新的PowerAdviser流程

SANTA CLARA, Calif. –– January 19, 2010 –– Calypto® Design Systems Inc. (www.calypto.com), the leader in sequential analysis technology, today announced a new PowerAdviser Flow that enables designers to deliver the most power-optimized SoC designs possible.  Using sequential design information generated by Calypto’s popular PowerPro CG and PowerPro MG tools, the PowerAdviser Flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power. The award-winning PowerPro product family is used by the world’s leading SoC designers for networking, computer, consumer, and wireless applications.
 
“Our goal is to provide SoC designers with the most comprehensive RTL power optimization platform available, enabling the creation of devices with the lowest power consumption possible despite increasing design complexity,” said Tom Sandoval, chief executive officer of Calypto Design Systems. “With our PowerAdviser Flow, designers now have the capability to easily achieve their power goals through either automated or manual RTL optimization.”

PowerAdviser Flow Reduces Power Optimization Task Time from Days to Hours

Identification of RTL modifications for power savings can represent up to 50 percent of the total manual power optimization effort. The PowerAdviser Flow automates the process of thoroughly investigating power optimization opportunities in an RTL design using the visualization capability provided by Calypto’s PowerPro Analyzer tool.  Designers can therefore more quickly understand where to invest design time for power reduction. 

The PowerAdviser Flow presents design optimizations in the form of RTL changes, schematics, and textual descriptions. Quantifiable power savings for every potential optimization is provided in the form of a hyperlinked table.

Opportunities for power optimization are provided to the user based on three methods:

• Enable Expression Visualization : Displays enable expressions that are automatically generated by PowerPro.  The expressions can be directly inserted into the RTL by the designer.

• Enable Expression Assistance : Displays changes to the RTL that would result in the identification of additional clock gating/memory gating opportunities by PowerPro.  Once the changes to the RTL are made, PowerPro is rerun to generate the enable expressions that can be directly inserted into the RTL.

• MicroArchitecture Assistance: Identifies design regions using PowerPro generated statistics (power, clock-gating efficiency, toggle data, etc.) where micro-architectural modifications would result in identification of additional clock gating/memory gating opportunities by PowerPro.  Once the modifications are made, PowerPro is rerun to generate the enable expressions that can be directly inserted into the RTL.

Once the RTL changes are made, Calypto’s popular SLEC® RTL product is used to comprehensively verify that the new power-optimized RTL is functionally equivalent to the original RTL. 

PowerPro 3.1 Adds New Features Aimed at Power Optimization

The PowerAdviser Flow is available in the PowerPro 3.1 release.  In addition to the PowerAdviser Flow, the PowerPro 3.1 release includes new features and capabilities to reduce power in logic, registers, clocks, and embedded memories, including new sequential optimization techniques to reduce dynamic and leakage memory power, ECO support, and 64-bit support for optimizing larger designs.